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IPPS
2003
IEEE
15 years 11 months ago
Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
João M. P. Cardoso
IPPS
2003
IEEE
15 years 11 months ago
Flexible CoScheduling: Mitigating Load Imbalance and Improving Utilization of Heterogeneous Resources
Fine-grained parallel applications require all their processes to run simultaneously on distinct processors to achieve good efficiency. This is typically accomplished by space sl...
Eitan Frachtenberg, Dror G. Feitelson, Fabrizio Pe...
ISCAS
2003
IEEE
91views Hardware» more  ISCAS 2003»
15 years 11 months ago
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity
The full-custom CMOS realization of a new modular sorting architecture is presented. The high-performance architecture is based on rank ordering, and on efficient implementation o...
Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici
ISCAS
2003
IEEE
148views Hardware» more  ISCAS 2003»
15 years 11 months ago
Hybrid neural network architecture for age identification of ancient Kannada scripts
Wide research has been carried out and is still taking place in the field of character recognition of handwritten English characters. Recognizing English characters is much simple...
Harish K. Kashyap, Bansilal, P. Arun Koushik
ISCAS
2003
IEEE
98views Hardware» more  ISCAS 2003»
15 years 11 months ago
Minimum selection GSC and adaptive low-power rake combining scheme
In this paper, we investigate a new generalized selection combining (GSC) technique and an adaptive rake combining scheme to save the power consumption of mobile rake receivers fo...
Suk Won Kim, Dong Sam Ha, Jeffrey H. Reed