5762 search results - page 975 / 1153 » R-tree: A Hardware Implementation |
181
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IEEEPACT
2005
IEEE
16 years 5 days ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
189
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IPPS
2005
IEEE
16 years 5 days ago
2005
IEEE
Parallel random access memory, or PRAM, is a now venerable model of parallel computation that that still retains its usefulness for the design and analysis of parallel algorithms....
170
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IPPS
2005
IEEE
16 years 5 days ago
2005
IEEE
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
191
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ISCAS
2005
IEEE
16 years 5 days ago
2005
IEEE
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
125
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ISCAS
2005
IEEE
16 years 5 days ago
2005
IEEE
—A novel clock and data recovery architecture with adaptive loop gain is proposed for spread spectrum SerDes applications such as the Serial AT Attachment. The proposed design co...