5762 search results - page 968 / 1153 » R-tree: A Hardware Implementation |
132
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ISCAS
2006
IEEE
16 years 18 days ago
2006
IEEE
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...
162
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ISCAS
2006
IEEE
16 years 18 days ago
2006
IEEE
The H.264/AVC standard defines an in-loop de- instructions, available in current multimedia SIMD instruction blocking filter which is used in both the encoder and decoder. This set...
148
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ISCAS
2006
IEEE
16 years 18 days ago
2006
IEEE
—As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper...
125
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ISCAS
2006
IEEE
16 years 18 days ago
2006
IEEE
— Quadrature Σ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. If two separated multibit feedback DACs are used, mismatch among the...
178
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ISCAS
2006
IEEE
16 years 18 days ago
2006
IEEE
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...