Sciweavers

5762 search results - page 930 / 1153
» R-tree: A Hardware Implementation
Sort
View
CLUSTER
2009
IEEE
16 years 1 months ago
Power-aware scheduling of virtual machines in DVFS-enabled clusters
—With the advent of Cloud computing, large-scale virtualized compute and data centers are becoming common in the computing industry. These distributed systems leverage commodity ...
Gregor von Laszewski, Lizhe Wang, Andrew J. Younge...
IWMM
2009
Springer
166views Hardware» more  IWMM 2009»
16 years 1 months ago
Garbage collection in the next C++ standard
: © Garbage Collection in the Next C++ Standard Hans-J. Boehm, Mike Spertus HP Laboratories HPL-2009-360 C++, garbage collection C++ has traditionally relied on manual memory mana...
Hans-Juergen Boehm, Mike Spertus
NOSSDAV
2009
Springer
16 years 1 months ago
Random network coding on the iPhone: fact or fiction?
In multi-hop wireless networks, random network coding represents the general design principle of transmitting random linear combinations of blocks in the same “batch” to downs...
Hassan Shojania, Baochun Li
CASES
2009
ACM
16 years 1 months ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
CODES
2008
IEEE
16 years 1 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid