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ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
15 years 12 months ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
ISCA
2003
IEEE
104views Hardware» more  ISCA 2003»
15 years 12 months ago
Token Coherence: Decoupling Performance and Correctness
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
Milo M. K. Martin, Mark D. Hill, David A. Wood
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 12 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
SBACPAD
2003
IEEE
120views Hardware» more  SBACPAD 2003»
15 years 12 months ago
Comparison of Genomes Using High-Performance Parallel Computing
Comparison of the DNA sequences and genes of two genomes can be useful to investigate the common functionalities of the corresponding organisms and get a better understanding of h...
Nalvo F. Almeida Jr., Carlos E. R. Alves, Edson C&...
SBACPAD
2003
IEEE
138views Hardware» more  SBACPAD 2003»
15 years 12 months ago
Finite Difference Simulations of the Navier-Stokes Equations Using Parallel Distributed Computing
 This paper discusses the implementation of a numerical algorithm for simulating incompressible fluid flows based on the finite difference method and designed for parallel compu...
João Paulo De Angeli, Andréa M. P. V...