5762 search results - page 909 / 1153 » R-tree: A Hardware Implementation |
186
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MICRO
2006
IEEE
16 years 21 days ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
156
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MICRO
2006
IEEE
16 years 21 days ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
207
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ACMMSP
2006
ACM
16 years 20 days ago
2006
ACM
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...
161
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ACISICIS
2005
IEEE
16 years 9 days ago
2005
IEEE
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
166
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CODES
2005
IEEE
16 years 9 days ago
2005
IEEE
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...