5762 search results - page 905 / 1153 » R-tree: A Hardware Implementation |
277
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ASPLOS
2009
ACM
16 years 7 months ago
2009
ACM
While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on mu...
174
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HPCA
2009
IEEE
16 years 7 months ago
2009
IEEE
New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementatio...
174
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
172
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ICCAD
2002
IEEE
16 years 3 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
200
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FPGA
2009
ACM
16 years 1 months ago
2009
ACM
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...