Sciweavers

5762 search results - page 839 / 1153
» R-tree: A Hardware Implementation
Sort
View
178
Voted
IOLTS
2003
IEEE
138views Hardware» more  IOLTS 2003»
16 years 2 days ago
An Analog Checker With Input-Relative Tolerance for Duplicate Signals
We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. Th...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
ISCAS
2003
IEEE
117views Hardware» more  ISCAS 2003»
16 years 2 days ago
Learning temporal correlations in biologically-inspired aVLSI
Temporally-asymmetric Hebbian learning is a class of algorithms motivated by data from recent neurophysiology experiments. While traditional Hebbian learning rules use mean firin...
Adria Bofill-i-Petit, Alan F. Murray
ISCAS
2003
IEEE
153views Hardware» more  ISCAS 2003»
16 years 2 days ago
A VLSI model of range-tuned neurons in the bat echolocation system
The neural computations that support bat echolocation are of great interest to both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the ...
Matthew Cheely, Timothy K. Horiuchi
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
16 years 2 days ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek
ISCAS
2003
IEEE
98views Hardware» more  ISCAS 2003»
16 years 2 days ago
Dynamic operand transformation for low-power multiplier-accumulator design
: The design of portable battery-operated devices requires low-power computation circuits. This paper presents a new multiplier-accumulator (MAC) design approach, which in contrast...
Masayoshi Fujino, Vasily G. Moshnyaga