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129
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
133
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
130
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
We describe an algorithm for self-organizing connections from a source array to a target array of neurons that is inspired by neural growth cone guidance. Each source neuron proje...
149
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
143
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...