5762 search results - page 827 / 1153 » R-tree: A Hardware Implementation |
160
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
—Efficient routing schemes are essential if Network on Chip (NoC) architectures are to be used for implementing multi-core systems for real-time multi-media applications. These s...
198
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
Abstract— In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve...
179
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ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
— We discuss a distributed imaging architecture with active illumination for sensor network applications. An event-based CMOS imager is employed at the sensor level, to convert l...
129
Voted
ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
Abstract— Micro-pipelines are linear (1-D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2-D image regions is a key to efficie...
145
click to vote
ISCAS
2005
IEEE
16 years 12 days ago
2005
IEEE
— We propose a new crossbar switch structure with adaptive bandwidth control. In a complex SoC design, the proposed crossbar switch efficiently incorporates various IPs with diff...