5762 search results - page 822 / 1153 » R-tree: A Hardware Implementation |
123
click to vote
ISCAS
2006
IEEE
16 years 25 days ago
2006
IEEE
— By implementing an FPGA-based simulator, we investigate the performance of high-rate quasi-cyclic (QC) LDPC codes for the magnetic recording channel at very low sector error ra...
154
click to vote
ISCAS
2006
IEEE
16 years 25 days ago
2006
IEEE
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
146
click to vote
ISCAS
2006
IEEE
16 years 25 days ago
2006
IEEE
—We present an efficient approach for on-chip frequency response measurement, including phase and gain, of analog circuitry in mixed-signal systems. The approach uses direct digi...
161
click to vote
ISMVL
2006
IEEE
16 years 25 days ago
2006
IEEE
We define the MaxSAT problem for many-valued CNF formulas, called many-valued MaxSAT, and establish its complexity class. We then describe a basic branch and bound algorithm for ...
163
click to vote
ISVLSI
2006
IEEE
16 years 25 days ago
2006
IEEE
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...