5762 search results - page 815 / 1153 » R-tree: A Hardware Implementation |
161
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
128
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
—In the implementation of a few JPEG steganographic schemes such as OutGuess and F5, an additional JPEG compression may take place before data embedding. The effect of this recom...
148
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ISCAS
2007
IEEE
16 years 1 months ago
2007
IEEE
— A 2-MITE is a multiple-input translinear element with two input gates. In this paper, different properties of networks of 2-MITEs are derived, especially in the case of product...
172
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ISMVL
2007
IEEE
16 years 1 months ago
2007
IEEE
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
143
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MSS
2007
IEEE
16 years 1 months ago
2007
IEEE
As storage systems grow larger and more complex, the traditional block-based design of current disks can no longer satisfy workloads that are increasingly metadata intensive. A ne...