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PACS
2004
Springer
146views Hardware» more  PACS 2004»
16 years 7 days ago
An Optimized Front-End Physical Register File with Banking and Writeback Filtering
In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a ...
Miquel Pericàs, Rubén Gonzále...
CODES
2003
IEEE
16 years 5 days ago
Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and crypt
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
Wei Ming Lim, Mohammed Benaissa
MSS
2003
IEEE
98views Hardware» more  MSS 2003»
16 years 4 days ago
A Performance Analysis of the iSCSI Protocol
Fibre channel has long dominated the realm of storage area networks (SAN’s). However, with increased development and refining, iSCSI is fast becoming an equal contender, which ...
Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, ...
EWSN
2010
Springer
16 years 6 hour ago
Wiselib: A Generic Algorithm Library for Heterogeneous Sensor Networks
One unfortunate consequence of the success story of wireless sensor networks (WSNs) in separate research communities is an evergrowing gap between theory and practice. Even though ...
Tobias Baumgartner, Ioannis Chatzigiannakis, S&aac...
ASAP
2002
IEEE
170views Hardware» more  ASAP 2002»
15 years 12 months ago
Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
Peter Kornerup