Sciweavers

5762 search results - page 791 / 1153
» R-tree: A Hardware Implementation
Sort
View
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
15 years 8 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
DSD
2010
IEEE
140views Hardware» more  DSD 2010»
15 years 7 months ago
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
—Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtract...
Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos&...
JCP
2008
97views more  JCP 2008»
15 years 7 months ago
Profiling Tools for FPGA-Based Embedded Systems: Survey and Quantitative Comparison
Profiling tools are computer-aided design (CAD) tools that help in determining the computationally intensive portions in software. Embedded systems consist of hardware and software...
Jason G. Tong, Mohammed A. S. Khalid
JPDC
2006
111views more  JPDC 2006»
15 years 6 months ago
Designing irregular parallel algorithms with mutual exclusion and lock-free protocols
Irregular parallel algorithms pose a significant challenge for achieving high performance because of the difficulty predicting memory access patterns or execution paths. Within an...
Guojing Cong, David A. Bader
MICRO
2006
IEEE
107views Hardware» more  MICRO 2006»
15 years 6 months ago
Dataflow Predication
Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order microarchitecture...
Aaron Smith, Ramadass Nagarajan, Karthikeyan Sanka...