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FPL
2008
Springer
110views Hardware» more  FPL 2008»
15 years 8 months ago
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip
While there have been many reported implementations of Networks-on-Chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication ...
Matthew Shelburne, Cameron Patterson, Peter Athana...
FPL
2008
Springer
86views Hardware» more  FPL 2008»
15 years 8 months ago
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors
In multi-context Dynamically Reconfigurable Processor Array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such c...
Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Ha...
ISLPED
2007
ACM
75views Hardware» more  ISLPED 2007»
15 years 8 months ago
Minimizing power dissipation during write operation to register files
This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementar...
Kimish Patel, Wonbok Lee, Massoud Pedram
DAGSTUHL
2007
15 years 8 months ago
QUAD: Overview and Recent Developments
We give an outline of the specification and provable security features of the QUAD stream cipher proposed at Eurocrypt 2006 [6]. The cipher relies on the iteration of a multivaria...
David Arditti, Côme Berbain, Olivier Billet,...
ERSA
2007
194views Hardware» more  ERSA 2007»
15 years 8 months ago
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Abstract: If the computational demands of an interactive graphics rendering application cannot be met by a single commodity Graphics Processing Unit (GPU), multiple graphics accele...
Ross Brennan, Michael Manzke, Keith O'Conor, John ...