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ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
15 years 9 months ago
Making fast buffer insertion even faster via approximation techniques
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang...
ATS
2005
IEEE
164views Hardware» more  ATS 2005»
15 years 9 months ago
A Family of Logical Fault Models for Reversible Circuits
Reversibility is of interest in achieving extremely low power dissipation; it is also an inherent design requirement of quantum computation. Logical fault models for conventional ...
Ilia Polian, Thomas Fiehn, Bernd Becker, John P. H...
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
15 years 9 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
15 years 8 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
ECBS
2007
IEEE
161views Hardware» more  ECBS 2007»
15 years 8 months ago
Alert Fusion for a Computer Host Based Intrusion Detection System
Intrusions impose tremendous threats to today’s computer hosts. Intrusions using security breaches to achieve unauthorized access or misuse of critical information can have cata...
Chuan Feng, Jianfeng Peng, Haiyan Qiao, Jerzy W. R...