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EUC
2006
Springer
15 years 10 months ago
A Processor Extension for Cycle-Accurate Real-Time Software
Certain hard real-time tasks demand precise timing of events, but the usual software solution of periodic interrupts driving a scheduler only provides precision in the millisecond ...
Nicholas Jun Hao Ip, Stephen A. Edwards
FPL
2006
Springer
96views Hardware» more  FPL 2006»
15 years 10 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
FPL
2006
Springer
125views Hardware» more  FPL 2006»
15 years 10 months ago
Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique
Many compute-intensive applications generate single result values by accessing clusters of nearby points in grids of one, two, or more dimensions. Often, the performance of FGPA i...
Tom Van Court, Martin C. Herbordt
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
15 years 10 months ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...
ACSD
2003
IEEE
105views Hardware» more  ACSD 2003»
15 years 10 months ago
Detecting State Coding Conflicts in STG Unfoldings Using SAT
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev