5762 search results - page 771 / 1153 » R-tree: A Hardware Implementation |
154
click to vote
ISCA
1989
IEEE
15 years 11 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
159
click to vote
ASPDAC
2009
ACM
15 years 11 months ago
2009
ACM
The post-T/pre-T trace refers to the trace captured before/after a target point is reached, respectively. Real time compression of the post-T trace in a circular buffer is a challe...
168
click to vote
ARC
2007
Springer
15 years 11 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
179
click to vote
ASPDAC
2007
ACM
15 years 11 months ago
2007
ACM
Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such de...
166
Voted
ASPDAC
2007
ACM
15 years 11 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...