5762 search results - page 762 / 1153 » R-tree: A Hardware Implementation |
179
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ICCAD
1999
IEEE
15 years 11 months ago
1999
IEEE
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
187
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ICCAD
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
199
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ICCD
1999
IEEE
15 years 11 months ago
1999
IEEE
Current trends in DRAM memory chip fabrication have led many researchers to propose \intelligent memory" architectures that integrate microprocessors or logic with memory. Su...
254
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CAV
1999
Springer
15 years 11 months ago
1999
Springer
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. A computation that violates a general linea...
191
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ISCA
1999
IEEE
15 years 11 months ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...