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ISLPED
1999
ACM
236views Hardware» more  ISLPED 1999»
15 years 11 months ago
Modeling and automating selection of guarding techniques for datapath elements
While guarded evaluation has proven an effective energy saving technique in arithmetic circuits, good methodologies do not exist for determining when and how to guard for maximal ...
William E. Dougherty, Donald E. Thomas
ISPD
1999
ACM
89views Hardware» more  ISPD 1999»
15 years 11 months ago
VIA design rule consideration in multi-layer maze routing algorithms
—Maze routing algorithms are widely used for finding an optimal path in detailed routing for very large scale integration, printed circuit board and multichip modules In this pap...
Jason Cong, Jie Fang, Kei-Yong Khoo
DATE
1999
IEEE
139views Hardware» more  DATE 1999»
15 years 11 months ago
OpenJ: An Extensible System Level Design Language
There is an increasing research interest in system level design languages which can carry designers from specification to implementation of system-on-a-chip. Unfortunately, two of...
Jianwen Zhu, Daniel Gajski
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 11 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
15 years 11 months ago
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. A recent algorit...
Robert M. Fuhrer, Steven M. Nowick