5762 search results - page 756 / 1153 » R-tree: A Hardware Implementation |
184
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ASYNC
2000
IEEE
15 years 11 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
183
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ATS
2000
IEEE
15 years 11 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
205
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
193
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are t...
170
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...