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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 12 months ago
E-Design Based on the Reuse Paradigm
This paper gives an overview on a Virtual electronic component or IP (Intellectual Property) exchange infrastructure whose main components are a XML "well structured IP e-cat...
L. Ghanmi, A. Ghrab, M. Hamdoun, B. Missaoui, K. S...
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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 12 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
IOLTS
2002
IEEE
99views Hardware» more  IOLTS 2002»
15 years 12 months ago
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
Davide Appello, Alessandra Fudoli, Vincenzo Tancor...
ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
15 years 12 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 12 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...