5762 search results - page 746 / 1153 » R-tree: A Hardware Implementation |
195
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MICRO
2003
IEEE
16 years 9 days ago
2003
IEEE
Traditional software controlled data cache prefetching is often ineffective due to the lack of runtime cache miss and miss address information. To overcome this limitation, we imp...
185
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MICRO
2003
IEEE
16 years 9 days ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
198
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MTV
2003
IEEE
16 years 9 days ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
174
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SBACPAD
2003
IEEE
16 years 9 days ago
2003
IEEE
— Scheduling by Edge Reversal (SER) is a fully distributed scheduling mechanism based on the manipulation of acyclic orientations of a graph. This work uses SER to perform constr...
174
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ISLPED
2003
ACM
16 years 8 days ago
2003
ACM
Memory systems consume a significant portion of power in handheld embedded systems. So far, low-power memory techniques have addressed the power consumption when the system is tu...