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DATE
2005
IEEE
115views Hardware» more  DATE 2005»
16 years 20 days ago
Stochastic Power Grid Analysis Considering Process Variations
In this paper, we investigate the impact of interconnect and device process variations on voltage fluctuations in power grids. We consider random variations in the power grid’s...
Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Pa...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
16 years 20 days ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
DATE
2005
IEEE
106views Hardware» more  DATE 2005»
16 years 20 days ago
SAT-Based Complete Don't-Care Computation for Network Optimization
This paper describes an improved approach to Boolean network optimization using internal don’t-cares. The improvements concern the type of don’t-cares computed, their scope, a...
Alan Mishchenko, Robert K. Brayton
DATE
2005
IEEE
146views Hardware» more  DATE 2005»
16 years 20 days ago
Nonuniform Banking for Reducing Memory Energy Consumption
Main memories can consume a large percentage of overall energy in many data-intensive embedded applications. The past research proposed and evaluated memory banking as a possible ...
Ozcan Ozturk, Mahmut T. Kandemir
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
16 years 20 days ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...