5762 search results - page 728 / 1153 » R-tree: A Hardware Implementation |
175
click to vote
DSD
2006
IEEE
16 years 1 months ago
2006
IEEE
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
189
click to vote
DSD
2006
IEEE
16 years 1 months ago
2006
IEEE
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
155
click to vote
DSD
2006
IEEE
16 years 1 months ago
2006
IEEE
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
152
click to vote
DSN
2006
IEEE
16 years 1 months ago
2006
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
204
click to vote
FCCM
2006
IEEE
16 years 1 months ago
2006
IEEE
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...