Sciweavers

5762 search results - page 719 / 1153
» R-tree: A Hardware Implementation
Sort
View
ISQED
2008
IEEE
154views Hardware» more  ISQED 2008»
16 years 1 months ago
Error Protected Data Bus Inversion Using Standard DRAM Components
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
Maurizio Skerlj, Paolo Ienne
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
16 years 1 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
SASP
2008
IEEE
140views Hardware» more  SASP 2008»
16 years 1 months ago
An FPGA Design Space Exploration Tool for Matrix Inversion Architectures
— Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communic...
Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan ...
SBACPAD
2008
IEEE
132views Hardware» more  SBACPAD 2008»
16 years 1 months ago
Aspect-Based Patterns for Grid Programming
The development of grid algorithms is frequently hampered by limited means to describe topologies and lack of support for the invasive composition of legacy components in order to...
Luis Daniel Benavides Navarro, Rémi Douence...
SBACPAD
2008
IEEE
249views Hardware» more  SBACPAD 2008»
16 years 1 months ago
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture
This work presents an implementation of Neocognitron Neural Network, using a high performance computing architecture based on GPU (Graphics Processing Unit). Neocognitron is an ar...
Gustavo Poli, José Hiroki Saito, Joã...