5762 search results - page 696 / 1153 » R-tree: A Hardware Implementation |
182
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MICRO
2003
IEEE
16 years 11 days ago
2003
IEEE
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
210
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CF
2010
ACM
16 years 5 days ago
2010
ACM
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
250
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RT
2001
Springer
15 years 11 months ago
2001
Springer
This paper presents a technique for representing and displaying high dynamic-range texture maps (HDRTMs) using current graphics hardware. Dynamic range in real-world environments o...
213
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IEEEPACT
1998
IEEE
15 years 11 months ago
1998
IEEE
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...
192
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MICRO
1998
IEEE
15 years 11 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...