5762 search results - page 691 / 1153 » R-tree: A Hardware Implementation |
192
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DATE
2003
IEEE
16 years 12 days ago
2003
IEEE
ng precision of abstract SystemC models using the SystemC Verification Standard Franco Carbognani1 , Christopher K. Lennard2 , C. Norris Ip3 , Allan Cochrane2 , Paul Bates2 1 Caden...
198
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FCCM
2003
IEEE
16 years 12 days ago
2003
IEEE
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
199
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ISCA
1996
IEEE
15 years 11 months ago
1996
IEEE
Parallel workstations, each comprising 10-100 processors, promise cost-effective general-purpose multiprocessing. This paper explores the coupling of such small- to medium-scale s...
211
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
221
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EUROPAR
2008
Springer
15 years 8 months ago
2008
Springer
Over the last decade, Message Passing Interface (MPI) has become a very successful parallel programming environment for distributed memory architectures such as clusters. However, ...