Sciweavers

5762 search results - page 679 / 1153
» R-tree: A Hardware Implementation
Sort
View
CAV
2006
Springer
165views Hardware» more  CAV 2006»
15 years 11 months ago
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
Many multithreaded programs employ concurrent data types to safely share data among threads. However, highly-concurrent algorithms for even seemingly simple data types are difficul...
Sebastian Burckhardt, Rajeev Alur, Milo M. K. Mart...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 7 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
INTEGRATION
2007
100views more  INTEGRATION 2007»
15 years 7 months ago
A fast pipelined multi-mode DES architecture operating in IP representation
The Data Encryption Standard (DES) is a cipher that is still used in a broad range of applications, from smartcards, where it is often implemented as a tamperresistant embedded co...
Sylvain Guilley, Philippe Hoogvorst, Renaud Pacale...
MOBISYS
2011
ACM
14 years 10 months ago
Exploiting FM radio data system for adaptive clock calibration in sensor networks
Clock synchronization is critical for Wireless Sensor Networks (WSNs) due to the need of inter-node coordination and collaborative information processing. Although many message pa...
Liqun Li, Guoliang Xing, Limin Sun, Wei Huangfu, R...
ICFP
2009
ACM
16 years 7 months ago
Runtime support for multicore Haskell
Purely functional programs should run well on parallel hardware because of the absence of side effects, but it has proved hard to realise this potential in practice. Plenty of pap...
Simon Marlow, Simon L. Peyton Jones, Satnam Singh