5762 search results - page 672 / 1153 » R-tree: A Hardware Implementation |
168
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TC
2008
15 years 7 months ago
2008
A high performance architecture of elliptic curve scalar multiplication over finite field GF(2m ) is proposed. A pseudo-pipelined word serial finite field multiplier with word siz...
148
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TSP
2008
15 years 7 months ago
2008
This paper presents methods for independently modifying the time and pitch scale of acoustic signals, with an emphasis on speech signals. The algorithms developed here use paramet...
166
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TSP
2008
15 years 7 months ago
2008
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) dec...
224
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ICCAD
2008
IEEE
16 years 4 months ago
2008
IEEE
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...
197
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ASPLOS
2010
ACM
16 years 2 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...