5762 search results - page 659 / 1153 » R-tree: A Hardware Implementation |
183
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TAP
2007
Springer
16 years 1 months ago
2007
Springer
We present a new automatic test generation method for JAVA CARD based on attempts at formal verification of the implementation under test (IUT). Self-contained unit tests in JUnit...
182
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FCCM
2006
IEEE
16 years 1 months ago
2006
IEEE
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
158
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IMSCCS
2006
IEEE
16 years 1 months ago
2006
IEEE
The computer architecture of Single-chip multiprocessor (SCMP) is one of important research topics in developing the next-generation of computer hardware. A verification environme...
161
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IOLTS
2006
IEEE
16 years 1 months ago
2006
IEEE
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
140
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ISCAS
2006
IEEE
16 years 1 months ago
2006
IEEE
—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully in...