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IOLTS
2006
IEEE
84views Hardware» more  IOLTS 2006»
16 years 1 months ago
An Improved Technique for Reducing False Alarms Due to Soft Errors
A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every ...
Sandip Kundu, Ilia Polian
ISCAS
2006
IEEE
147views Hardware» more  ISCAS 2006»
16 years 1 months ago
Triangular systolic array with reduced latency for QR-decomposition of complex matrices
- The novel CORDIC-based architecture of the these weights (combiner unit). The implementation of the Triangular Systolic Array for QRD of large size complex combiner unit is rathe...
Alexander Maltsev, V. Pestretsov, Roman Maslenniko...
ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
16 years 1 months ago
Fast bit permutation unit for media enhanced microprocessors
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-...
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, ...
ISCAS
2006
IEEE
84views Hardware» more  ISCAS 2006»
16 years 1 months ago
Programmable synaptic weights for an aVLSI network of spiking neurons
—We describe a spiking neuronal network which allows local synaptic weights to be assigned to individual synapses. In previous implementations of neuronal networks, the biases th...
Yingxue Wang, Shih-Chii Liu
ISCAS
2006
IEEE
114views Hardware» more  ISCAS 2006»
16 years 1 months ago
System for deposition and characterization of polypyrrole/gold bilayer hinges
— We report on a custom designed system for the deposition and characterization of polypyrrole bilayer actuators. Unlike conventional commercial electrochemical cells and potenti...
Edward Choi, Yingkai Liu, Elisabeth Smela, Andreas...