5762 search results - page 622 / 1153 » R-tree: A Hardware Implementation |
174
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MICRO
2000
IEEE
15 years 10 months ago
2000
IEEE
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
201
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CAV
1997
Springer
15 years 10 months ago
1997
Springer
We demonstrate the feasibility of using the XSB tabled logic programming system as a programmable fixed-point engine for implementing efficient local model checkers. In particular,...
207
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ISLPED
1995
ACM
15 years 10 months ago
1995
ACM
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL . Such a high-level power estimation capability is r...
224
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MICRO
1995
IEEE
15 years 10 months ago
1995
IEEE
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
202
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CAV
2008
Springer
15 years 9 months ago
2008
Springer
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...