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FPL
2006
Springer
161views Hardware» more  FPL 2006»
15 years 11 months ago
Predictive Load Balancing for Interconnected FPGAs
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...
Jason D. Bakos, Charles L. Cathey, Allen Michalski
FPL
2006
Springer
158views Hardware» more  FPL 2006»
15 years 11 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
FPL
2006
Springer
140views Hardware» more  FPL 2006»
15 years 11 months ago
Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs
FPGAs have reached densities that can implement floatingpoint applications, but floating-point operations still require a large amount of FPGA resources. One major component of IE...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
FPL
2006
Springer
124views Hardware» more  FPL 2006»
15 years 11 months ago
A Dynamically Reconfigurable Queue Scheduler
In this paper we present the design and implementation of a dynamically reconfigurable system for packet queue scheduling. Two widely accepted queue schedulers have been implement...
Christoforos Kachris, Stamatis Vassiliadis
IWMM
2000
Springer
105views Hardware» more  IWMM 2000»
15 years 10 months ago
Diffusion Tree Restructuring for Indirect Reference Counting
A new variant algorithm for distributed acyclic garbage detection is presented for use in hybrid garbage collectors. The existing fault-tolerance of Piquer's Indirect Referen...
Peter Dickman