5762 search results - page 617 / 1153 » R-tree: A Hardware Implementation |
169
Voted
ITC
1996
IEEE
15 years 11 months ago
1996
IEEE
Orthogonal scan paths, which follow the path of the data flow, can be used in data path designs to reduce the test overhead -- area, delay and test application time -- by sharing ...
198
Voted
ICCAD
1993
IEEE
15 years 11 months ago
1993
IEEE
Circuit simulation is one of the most computationally expensive tasks in circuit design and optimization. Detailed simulation at the level of precision of SPICE is usually perform...
181
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
We propose new techniques for efficient breadth-first iterative manipulation of ROBDDs. Breadth-first iterative ROBDD manipulation can potentially reduce the total elapsed time by...
175
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
205
Voted
IPPS
1994
IEEE
15 years 11 months ago
1994
IEEE
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...