5762 search results - page 604 / 1153 » R-tree: A Hardware Implementation |
186
Voted
DATE
2006
IEEE
16 years 1 months ago
2006
IEEE
Enhancing productivity for designing complex embedded systems requires system level design methodology and language support for capturing complex design in high level models. For ...
182
click to vote
ETS
2006
IEEE
16 years 1 months ago
2006
IEEE
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
185
click to vote
ISCA
2006
IEEE
16 years 1 months ago
2006
IEEE
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with...
168
click to vote
MICRO
2006
IEEE
16 years 1 months ago
2006
IEEE
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
194
click to vote
VLSID
2006
IEEE
16 years 1 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...