5762 search results - page 598 / 1153 » R-tree: A Hardware Implementation |
211
Voted
ICCAD
2007
IEEE
16 years 4 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
149
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ICCAD
2006
IEEE
16 years 4 months ago
2006
IEEE
— Methods for assembling crossbars from nanowires (NWs) have been designed and implemented. Methods for controlling individual NWs within a crossbar have also been proposed, but ...
193
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ICCAD
2005
IEEE
16 years 4 months ago
2005
IEEE
In this paper we propose a novel analog design optimization methodology to address two key aspects of top-down system-level design: (1) how to optimally compare and select analog ...
225
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ICCAD
2003
IEEE
16 years 4 months ago
2003
IEEE
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
187
Voted
FPGA
2010
ACM
16 years 4 months ago
2010
ACM
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...