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195
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CGF
2008
139views more  CGF 2008»
15 years 7 months ago
CHC++: Coherent Hierarchical Culling Revisited
We present a new algorithm for efficient occlusion culling using hardware occlusion queries. The algorithm significantly improves on previous techniques by making better use of te...
Oliver Mattausch, Jirí Bittner, Michael Wim...
CAL
2006
15 years 7 months ago
Probabilistic counter updates for predictor hysteresis and bias
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor de...
Nicholas Riley, Craig B. Zilles
157
Voted
CII
2006
141views more  CII 2006»
15 years 7 months ago
FPGA-based tool path computation: An application for shoe last machining on CNC lathes
Tool path generation is one of the most complex problems in Computer Aided Manufacturing. Although some efficient strategies have been developed, most of them are only useful for s...
Antonio Jimeno, José Luis Sánchez, H...
TVLSI
2008
119views more  TVLSI 2008»
15 years 7 months ago
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Katherine Compton, Scott Hauck
211
Voted
TVLSI
2008
115views more  TVLSI 2008»
15 years 7 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...