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ISCA
1994
IEEE
93views Hardware» more  ISCA 1994»
15 years 11 months ago
RAID-II: A High-Bandwidth Network File Server
In 1989, the RAID (Redundant Arrays of Inexpensive Disks) group at U. C. Berkeley built a prototype disk array called RAID-I. The bandwidth delivered to clients by RAID-I was seve...
Ann L. Drapeau, Ken Shirriff, John H. Hartman, Eth...
227
Voted
ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 11 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
157
Voted
ASAP
2007
IEEE
203views Hardware» more  ASAP 2007»
15 years 11 months ago
Reconfigurable Universal Adder
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
Humberto Calderon, Georgi Gaydadjiev, Stamatis Vas...
195
Voted
ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
15 years 11 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar
192
Voted
CASES
2007
ACM
15 years 11 months ago
A self-maintained memory module supporting DMM
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management (DMM); however, it is a challeng...
Weixing Ji, Feng Shi, Baojun Qiao