5762 search results - page 586 / 1153 » R-tree: A Hardware Implementation |
186
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FPL
2009
Springer
15 years 12 months ago
2009
Springer
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
185
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FPL
2001
Springer
15 years 11 months ago
2001
Springer
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between...
178
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CODES
2000
IEEE
15 years 11 months ago
2000
IEEE
Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and ...
160
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
177
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ITC
2000
IEEE
15 years 11 months ago
2000
IEEE
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...