5762 search results - page 569 / 1153 » R-tree: A Hardware Implementation |
216
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ICCAD
2009
IEEE
15 years 5 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
208
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ICCAD
2009
IEEE
15 years 5 months ago
2009
IEEE
A parallel computing approach for large-scale SPICE-accurate circuit simulation is described that is based on a new preconditioned iterative solver. The preconditioner involves the...
297
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SIGOPS
2011
15 years 2 months ago
2011
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
267
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SIGOPS
2010
15 years 2 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
212
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ISCA
2011
IEEE
14 years 11 months ago
2011
IEEE
Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric...