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ATS
2001
IEEE
137views Hardware» more  ATS 2001»
15 years 11 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
CAV
2000
Springer
125views Hardware» more  CAV 2000»
15 years 11 months ago
Efficient Reachability Analysis of Hierarchical Reactive Machines
Hierarchical state machines is a popular visual formalism for software specifications. To apply automated analysis to such specifications, the traditional approach is to compile th...
Rajeev Alur, Radu Grosu, Michael McDougall
EH
2000
IEEE
84views Hardware» more  EH 2000»
15 years 11 months ago
Evolutionary Design of Single Electron Systems
The differences between electronics design through artificial evolution and through conventional methods have the consequence that evolved circuits may take unusual leverage from ...
Adrian Thompson, Christoph Wasshuber
FPL
2000
Springer
77views Hardware» more  FPL 2000»
15 years 11 months ago
Multiple-Wordlength Resource Binding
This paper describes a novel resource binding technique for use in multiple-wordlength systems implemented in FPGAs. It is demonstrated that the multiple-wordlength binding problem...
George A. Constantinides, Peter Y. K. Cheung, Wayn...
FPL
2000
Springer
130views Hardware» more  FPL 2000»
15 years 11 months ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...