5762 search results - page 549 / 1153 » R-tree: A Hardware Implementation |
148
Voted
ISCAS
1994
IEEE
15 years 11 months ago
1994
IEEE
FIR ( nite impulse response) lters are widely used in digital signal processing. In this paper new architectures for high speed FIR lters with programmable coe cients are presente...
179
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DAC
1992
ACM
15 years 11 months ago
1992
ACM
This paper describes a model for, and an implementation of, production-based synthesis of hardware description language (HDL) code in which the overall structure of the resultant ...
229
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ICCD
1992
IEEE
15 years 11 months ago
1992
IEEE
Current synthesis methodologies based on hardwaredescription languages focus mainly on two distinct levels: behavior and register-transfer levels. In many practical cases, however...
154
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ICCD
1992
IEEE
15 years 11 months ago
1992
IEEE
We describe a new synthesis procedure for designing asynchronous controllers from burst-mode specifications, a class of specifications allowing multiple input change fundamental m...
213
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ASPDAC
2007
ACM
15 years 11 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...