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FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
16 years 12 days ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
ARCS
2004
Springer
16 years 9 days ago
Modelling Cryptonite - On the Design of a Programmable High-Performance Crypto Processor
: Cryptographic algorithms – even when designed for easy implementability on general purpose architectures – still show a huge performance gap between implementations in softwa...
Rainer Buchty
FPL
2004
Springer
95views Hardware» more  FPL 2004»
16 years 8 days ago
Increasing Pipelined IP Core Utilization in Process Networks Using Exploration
At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platf...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
DATE
2003
IEEE
86views Hardware» more  DATE 2003»
16 years 5 days ago
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
Temporal specification languages provide an efficient way to express events comprised of complex temporal scenarios. Assertions based on these languages are used to detect viola...
Avi Ziv
DATE
2003
IEEE
180views Hardware» more  DATE 2003»
16 years 5 days ago
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
Frank Gilbert, Michael J. Thul, Norbert Wehn