5762 search results - page 409 / 1153 » R-tree: A Hardware Implementation |
226
click to vote
MICRO
2003
IEEE
16 years 4 days ago
2003
IEEE
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
163
click to vote
DAC
2003
ACM
16 years 7 months ago
2003
ACM
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
174
click to vote
DAC
2005
ACM
16 years 7 months ago
2005
ACM
This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the conf...
185
click to vote
ICCD
2006
IEEE
16 years 3 months ago
2006
IEEE
—Reducing energy consumption is an important issue for battery powered embedded computing systems. Content Addressable Memory (CAM)-based Highly-Associative Caches (HAC) are wide...
206
click to vote
ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...