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190
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ISCA
1992
IEEE
111views Hardware» more  ISCA 1992»
15 years 11 months ago
Lazy Release Consistency for Software Distributed Shared Memory
Relaxed memory consistency models, such as release consistency, were introduced in order to reduce the impact of remote memory access latency in both software and hardware distrib...
Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel
ASAP
2007
IEEE
150views Hardware» more  ASAP 2007»
15 years 11 months ago
Customizing Reconfigurable On-Chip Crossbar Scheduler
We present a design of a customized crossbar scheduler for on-chip networks. The proposed scheduler arbitrates on-demand interconnects, where physical topologies are identical to ...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
FPL
2009
Springer
100views Hardware» more  FPL 2009»
15 years 10 months ago
A virus scanning engine using a parallel finite-input memory machine and MPUs
This paper presents a virus scanning engine. After showing the difference between ClamAV (an anti-virus software) and SNORT (an intrusion detection software), we show a new archit...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...
ASAP
2004
IEEE
123views Hardware» more  ASAP 2004»
15 years 10 months ago
A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these al...
Fabien Castanier, Alberto Ferrante, Vincenzo Piuri
181
Voted
ARCS
2006
Springer
15 years 10 months ago
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks
Abstract. Dynamic hardware reconfiguration is becoming a key technology in embedded system design that offers among others new potentials in dependable computing. To make system de...
Dirk Koch, Thilo Streichert, Steffen Dittrich, Chr...