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DSD
2008
IEEE
95views Hardware» more  DSD 2008»
16 years 1 months ago
Programmable Numerical Function Generators for Two-Variable Functions
This paper proposes a design method and programmable architectures for numerical function generators (NFGs) of two-variable functions. To realize a two-variable function in hardwa...
Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao
ICECCS
2008
IEEE
203views Hardware» more  ICECCS 2008»
16 years 1 months ago
Using AADL to Model a Protocol Stack
In recent trends, the Architecture Analysis and Design Language (AADL) has received increasing attention from safety-critical software development industries. Specific about the A...
Didier Delanote, Stefan Van Baelen, Wouter Joosen,...
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
16 years 1 months ago
Algorithm for parallel inverse halftoning using partitioning of Look-Up Table (LUT)
— The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this work we propose a new algorithm to ...
Umair F. Siddiqi, Sadiq M. Sait
ISCAS
2008
IEEE
141views Hardware» more  ISCAS 2008»
16 years 1 months ago
Reduced Z-datapath Cordic Rotator
In this article we propose a novel scheme based on virtually scaling-free COordinate Rotation DIgital Computer (CORDIC) algorithm to design a hardware efficient CORDIC rotator. Fo...
Koushik Maharatna, Karim El-Shabrawy, Bashir M. Al...
DAMON
2007
Springer
16 years 1 months ago
Parallel buffers for chip multiprocessors
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
John Cieslewicz, Kenneth A. Ross, Ioannis Giannaka...