5762 search results - page 390 / 1153 » R-tree: A Hardware Implementation |
201
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IPPS
2003
IEEE
16 years 3 days ago
2003
IEEE
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
195
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EH
2002
IEEE
15 years 11 months ago
2002
IEEE
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...
183
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MICRO
2000
IEEE
15 years 11 months ago
2000
IEEE
Value prediction breaks data dependencies in a program thereby creating instruction level parallelism that can increase program performance. Hardware based value prediction techni...
150
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ISCA
1998
IEEE
15 years 11 months ago
1998
IEEE
A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory ac...
148
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ISCA
1993
IEEE
15 years 11 months ago
1993
IEEE
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...