5762 search results - page 386 / 1153 » R-tree: A Hardware Implementation |
174
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DATE
2003
IEEE
16 years 4 days ago
2003
IEEE
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional...
157
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FPL
2003
Springer
16 years 1 days ago
2003
Springer
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
182
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
179
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
As FPGA devices become larger, more coarse-grain modules coupled with large scale reconfigurable fabric become available, thus enabling new classes of applications to run effici...
148
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IJCNN
2000
IEEE
15 years 11 months ago
2000
IEEE
In this paper, we propose a method to design a neural network(NN) by using a genetic algorithm(GA) and simulated annealing(SA). And also, in order to demonstrate the effectivenes...