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VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
16 years 7 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
ICCD
2006
IEEE
132views Hardware» more  ICCD 2006»
16 years 3 months ago
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
HICSS
2007
IEEE
120views Biometrics» more  HICSS 2007»
16 years 1 months ago
A Model-Based Approach for Platform-Independent Binary Components with Precise Timing and Fine-Grained Concurrency
Fine grained concurrency and accurate timing can be essential for embedded hardware and software systems. These requirements should be reflected in the specification and must be c...
Tim Schattkowsky, Gregor Engels, Alexander Fö...
GLVLSI
2006
IEEE
126views VLSI» more  GLVLSI 2006»
16 years 27 days ago
Hardware/software partitioning of operating systems: a behavioral synthesis approach
In this paper we propose a hardware real time operating system (HW-RTOS) solution that makes use of a dedicated hardware in order to replace the standard support provided by the P...
Sathish Chandra, Francesco Regazzoni, Marcello Laj...
IWSOC
2005
IEEE
133views Hardware» more  IWSOC 2005»
16 years 12 days ago
Design Mapping, and Simulations of a 3G WCDMA/FDD Basestation Using Network on Chip
This paper presents a case study of a single-chip 3G WCDMA/FDD basestation implementation based on a circuit-switched network on chip. As the amount of transistors on a chip conti...
Daniel Wiklund, Dake Liu